Transmitters are an indispensable component for radios, which have been used in cellular phones, indoor wireless local area networks (LAN) and wireless controllers. Due to emerging multi-mode and multi-band applications, a transmitter with wide-band coverage becomes necessary. Many applications require transmitters to switch rapidly between frequency bands, which impose a significant challenge to the transmitter solution.
A variety of wide-band transmitters are known. However, some of these include local oscillator (LO) based transmitters. The switching time of the LO based transmitter is often determined by the LO channel switching time under the governance of the loop bandwidth of the frequency synthesizer, which is typically around 1 MHz. Hence, the achievable channel switching time is several micro seconds which is too long of a time to be used in an agile radio application.
Alternatively, a fully digital Pulse-Width-Modulation (PWM) based multi-standard transmitter has been used. However, this PWM transmitter suffers from high distortion, and the channel switching time is still determined by the LO at the carrier frequency. As part of the evolution of multi-mode, multi-band transmitters, Direct Digital Synthesizers (DDS) have been used as the LO source to enhance switching speed, but they consume significant power and may not deliver a very high frequency LO with low spur. Another approach to get broadband coverage with fast band switching is the use of single sideband mixers to generate a number of LOs with different center frequency using a common Phase-locked loop (PLL), the channel switching time of which is relatively fast compared to prior techniques. However, this approach can only support a limited number of LO options and any additional channel mandates an addition of extra mixers.
As part of this evolution to support rapidly switching multi-band transmitters, delta-sigma modulators have been proposed to feed the RF transmitters. FIG. 1a illustrates such a bandpass delta-sigma-modulator (BDSM) 10 receiving an RF input 12 as part of an RF transmitter 1 logic. A common clock 14 drives the BDSM 10 and the modulated output of the BDSM 10 is amplified through a Power Amplifier (PA) 16 and passed through a bandpass filter 18 before being transmitted. However, the BDSM 10 in FIG. 1a cannot provide a very high dynamic range and/or wide-band operation due to a moderate clock frequency driving the BDSM 10. The clock frequency is constrained by technology and becomes a limiting factor in providing a high dynamic range or a wide-band operation in these transmitters. The limited dynamic range of such systems due to the limiting sampling clock rate does not meet even today's needs for narrow-band applications.
One of the recent techniques for a rapidly switching multi-band operation is the use of a time-interleaving, low-pass Digital-to-Analog Convertor (DAC) (shown as a circled area 102) in the transceiver 100, as illustrated in FIG. 1b. In the transmit path 114, the input data stream 103 is processed by a baseband processor 104 that generates an I and a Q for each incoming data element passed through a bank of time-interleaved DACs 106 and modulated by an intermediate frequency (IF) carrier frequency to create an IF signal 108. This IF signal 108 is taken through a Band Pass Filter (BPF) 110 and up-converted by a 60 GHz carrier frequency before being amplified by a PA 112 and transmitted via antenna 117. In this approach, higher performance at wider bandwidths than in FIG. 1a are reported. However, the architecture of FIG. 1b requires up conversion to generate the RF carrier. Latencies in LO switching times and fixed RF filter components are still bottlenecks to achieving fast band switching and further limit the reconfigurability of and usefulness in software-defined radio applications.
Referring now to FIGS. 1c-1f which discuss material from Galton, Ibid, a typical 2-bit Dynamic Element Matching (DEM) encoder DAC system encodes and/or permutes two bits of a thermometer coded digital signal at its output. The two thermometer coded bits can comprise one of the elements in {00, 01, 11} and DEM encoding can be accomplished by either randomly 1) swapping or 2) leaving in place the elements at the output, i.e. mapping the elements to the set {00, 01, 10, 11} at the output, as can be seen in FIG. 1c. A 2-bit digital signal 120 is received by a DEM Encoder 121, which encodes and separates the two bits into two digital signal paths 122 and 123, each carrying one bit that was swapped or left in place. The two digital signal paths are each received in parallel by two nominally identical 1-bit DACs 124 and 125, which can each comprise a single current switch (not shown). The two digital signals are each converted to analog signals and combined with a summing circuit 126 to produce a single outputted analog signal 127. Because the signals are summed, swapping the bits at the input of the DACs does not produce a different combined analog signal if the components within the two pathways are identical. Mismatch errors arise if the two 1-bit DACs 124 and 125 are not identical (or if components within the two pathways are not identical) and a resulting analog signal is generated containing a mismatch error in, for example, the output voltage v(t) of analog signal 127. This mismatch error can change in sign from positive to negative or negative to positive, when the bits in the aforementioned elements are swapped at the input of the DACs 124 and 125. This can be seen in graph 128 of FIG. 1d which depicts the output voltage y=v(t) being ε above or ε below the line that joins the output voltages at x=00 and x=11, where ε is the mismatch error at x=01 or 10. So, a typical 2-bit DEM would, when one of the bits of a 2-bit data signal is 1 and the other 0, either swap the bits or not swap the bits in a random, decision-making manner. Swapping them would change the sign of the mismatch error in the resulting analog signal when the digital signals are converted to analog and summed by the summing circuit. This sign in the mismatch error, which is here called s[n], can be generalized to be either +1, −1 or 0. The mismatch error can then be defined as:mismatch error≡emismatch=s[n]·eDAC[n]The equation above for a mismatch error contains the variable eDAC[n], which is either positive definite, or negative definite in this definition, and the variable's magnitude is equal to the magnitude of the mismatch error. The number [n] in this context is the sample number. The purpose of a DEM encoder is to alter the variable s[n] such that it is uncorrelated with the input of the 2 bits at the DACs, which will be described in more detail in the following paragraph.
As described in Galton 2010, Ibid, if the inputs of the 2 bits into the DEM encoder belong to the input sequence input [n]={01, 01, 00, 01, 11, 01}, one embodiment of a DEM encoder could map the sequence input [n] according to the following sequence of signs s[n]: {1, −1, 0, −1, 0, 1 . . . }, as can be seen in FIG. 1e where it is observed that the two bits 01 in input [0] are not switched (s[0]=1) and the bits in input [1] are switched (s[1]=−1). Subsequently, the bits 01 in input [3] are switched (s[3]=−1) and the bits in input [5] are not switched (s[5]=1). The sign s[n]=0 could be interpreted as the bits either 1) not being switched and/or 2) not being considered by the DEM encoder, and possibly re-routed around its components. For example, s[2]=0, which corresponds to input [2]=00. The two bits in input [2] are identical and they can either be not considered by the DEM encoder and re-routed around or within its components or they can be considered and not switched. This method of encoding the bits in a digital signal according to the sequences described above and in FIG. 1f is incorporated by mismatch-shaping DEM DAC systems which spectrally shape the mismatch noise.
The determination as to whether switching occurs or not for a given input[n] can be determined by the design of the DEM encoder. The determination can be described by one or a combination of the sequences of 1) switching at a first instance of an input 01 or 10 and not switching at the second instance thereof, 2) not switching at a first instance of an input 01 or 10 and switching at the second instance thereof, 3) a combination or sequence of these sequences, or 4) no apparent sequence, with a random selection of switching or not switching. The DEM encoder system can comprise multiplexers, flip-flops, random or pseudorandom bit generators, transistors, switches, and logic gates such as XOR gates, OR gates, NOR gates, XNOR gates, AND gates, NAND gates, NOT gates, etc. The DEM encoder system can comprise a programmable circuit such as a Field-Programmable Gate Array (FPGA). The generalization of the above-simplified algorithm can be applied to higher order bits and can be realized by someone skilled in the art. This can be exemplified by using several 2-bit DEM encoders for an N-bit length data signal or by using an N-bit DEM encoder, which would swap or not swap bits or portions of the inputted N-bit data according to the design of the N-bit encoder.
The field of multi-band, multi-mode RF transmitters is in need of modulating techniques that provide for wide-band operation with fast switching without requiring a very high sampling clock.